module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);

	localparam IDLE=3'b000;
	localparam S1=3'b001;//1
	localparam S2=3'b010;//11
	localparam S3=3'b011;//110
	localparam S4=3'b100;//1101,start_shifting=1
	
	reg [2:0]state;
	reg [2:0]next_state;
	always@(posedge clk)begin
		if(reset)begin
			state<=IDLE;
		end
		else begin
			state<=next_state;
		end
	end
	
	always@(*)begin
		case(state)
			IDLE:begin
				next_state=(data)?S1:IDLE;
			end
			S1:begin
				next_state=(data)?S2:IDLE;
			end
			S2:begin
				next_state=(data)?S2:S3;
			end
			S3:begin
				next_state=(data)?S4:IDLE;
			end
			S4:begin
				next_state=S4;
			end
		endcase
	end

assign start_shifting=state==S4;
	
endmodule